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mt9v022: 1/3-inch wide-vga digital image sensor features mt9v022_ds rev. l 6/15 en 1 ?semiconductor components industries, llc 2015, 1/3-inch wide-vga cmos digital image sensor mt9v022 datasheet, rev. l for the latest datasheet revision, please visit www.onsemi.com features ? array format: wide-vga, active 752h x 480v (360,960 pixels) ? global shutter photodiode pixels; simultaneous integration and readout ? monochrome or color: near_ir enhanced performance for use with non-visible nir illumination ? readout modes: progressive or interlaced ? shutter efficiency: >99% ? simple two-wire serial interface ? register lock capability ? window size: user programmable to any smaller format (qvga, cif, qcif, etc.). data rate can be maintained independent of window size ? binning: 2 x 2 and 4 x 4 of the full resolution ? adc: on-chip, 10-bit column-parallel (option to operate in 12-bit to 10-bit companding mode) ? automatic controls: auto exposure control (aec) and auto gain control (agc); variable regional and variable weight aec/agc ? support for four unique seri al control register ids to control multiple imagers on the same bus ? data output formats: ? single sensor mode: 10-bit parallel/stand-alone 8-bit or 10-bit serial lvds ? stereo sensor mode: interspersed 8-bit serial lvds applications ? automotive ? unattended surveillance ? stereo vision ?security ?smart vision ?automation ?video as input ?machine vision table 1: key performance parameters parameter value optical format 1/3-inch active imager size 4.51 mm (h) x 2.88 mm (v) 5.35 mm diagonal active pixels 752h x 480v pixel size 6.0 ? m x 6.0 ? m color filter array monochrome or color rgb bayer pattern shutter type global shutter maximum data rate/ master clock 26.6 mps/26.6 mhz full resolution 752 x 480 frame rate 60 fps (at full resolution) adc resolution 10-bit column-parallel responsivity 4.8 v/lux-sec (550nm) dynamic range >55 db linear; >80 db ? 100 db in hdr mode supply voltage 3.3 v + 0.3 v ?? all supplies) power consumption <320 mw at maximum data rate; 100 w standby power operating temperature -40c to +85c packaging 52-ball ibga, automotive-qualified; wafer or die
mt9v022_ds rev. l 6/15 en 2 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor ordering information ordering information see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documenta- tion, including information on evaluation kits, please visi t our web site at www.onsemi.com. table 2: available part numbers part number product description orderable product attribute description mt9v022ia7atc-dp rgb, 0deg cra, ibga package drypack, protective film MT9V022IA7ATC-DR rgb, 0deg cra, ibga package drypack mt9v022ia7atm-dp mono, 0deg cra, ibga package drypack, protective film mt9v022ia7atm-dr mono, 0deg cra, ibga package drypack mt9v022ia7atm-tp mono, 0deg cra, ibga package tape & reel, protective film mt9v022ia7atm-tr mono, 0deg cra, ibga package tape & reel
mt9v022_ds rev. l 6/15 en 3 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 color device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 two-wire serial interface sam ple read and write sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 appendix a ? serial configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 appendix b ? power-on reset and standby timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
mt9v022_ds rev. l 6/15 en 4 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: 52-ball ibga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical configuration (connection) ?parallel output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 7: timing example of pixel data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 8: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 9: timing diagram showing a write to r0x09 with the valu e 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10: timing diagram showing a read from r0x09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: timing diagram showing a bytewise write to r0x09 wi th the value 0x0284 . . . . . . . . . . . . . . . . . . . .18 figure 12: timing diagram showing a bytewise read from r0x 09; returned value 0x0284 . . . . . . . . . . . . . . . .18 figure 13: simultaneous master mo de synchronization waveforms #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 14: simultaneous master mo de synchronization waveforms #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 15: sequential master mode synchron ization waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 16: snapshot mode interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 17: snapshot mode frame synchronization waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 18: slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 19: signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 20: latency when changing integrat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 21: sequence of control voltages at the hdr gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 22: sequence of voltages in a piecewise linear pixel resp onse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 23: 12- to 10-bit companding chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 24: latency of analog gain change when agc is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 25: tiled sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 26: black level calibration flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 27: controllable and observable aec/agc registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 28: readout of six pixels in normal and column flip ou tput mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 29: readout of six rows in normal and row flip output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 30: readout of 8 pixels in normal and row bin output mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 31: readout of 8 pixels in normal and column bin output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 32: spatial illustration of interlaced image readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 33: different line_valid formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 34: serial output format for a 6x2 frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 35: propagation delays for pixclk and data out signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 36: propagation delays for frame_vali d and line_valid signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 figure 37: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 38: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 39: serial host interface data timing for write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 40: serial host interface data timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 41: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 42: acknowledge signal timing after an 8-bit read from th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 43: typical quantum efficiency?color. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 44: typical quantum efficiency?monoc hrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 45: 52-ball ibga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 46: stand-alone topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 47: stereoscopic topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 48: two-wire serial interface config uration in stereoscopic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 49: power-up, reset, clock and stan dby sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 50: standby restricted lo cation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
mt9v022_ds rev. l 6/15 en 5 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: frame time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 5: frame time?long integration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 6: slave address modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 7: lvds packet format in stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 8: lvds packet format in stereoscopy mode (stereoscopy mode bit asserted) . . . . . . . . . . . . . . . . . . .40 table 9: reserved words in the pixel data stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 10: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 11: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 12: ac electrical characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 13: performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
mt9v022_ds rev. l 6/15 en 6 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor general description general description the on semiconductor mt9v022 is a 1/3-in ch wide-vga format cmos active-pixel digital image sensor with global shutter an d high dynamic range (hdr) operation. the sensor has specifically been designed to support the demanding interior and exterior automotive imaging needs, which makes this part ideal for a wide variety of imaging applications in real-world environments. this wide-vga cmos image sensor featur es on semiconductor?s breakthrough low- noise cmos imaging technology that achiev es ccd image quality (based on signal-to- noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and inte- gration advantages of cmos. the active imaging pixel array is 752h x 480v. it incorporates sophisticated camera func- tions on-chip?such as binning 2 x 2 and 4 x 4, to improve sensitivity when operating in smaller resolutions?as well as windowing, column and row mirroring. it is program- mable through a simple two- wire serial interface. the mt9v022 can be operated in its default mode or be programmed for frame size, exposure, gain setting, and other paramete rs. the default mode outputs a wide-vga- size image at 60 fram es per second (fps). an on-chip analog-to-digital converter (adc) pr ovides 10 bits per pi xel. a 12-bit resolu- tion companded for 10 bits for small signals ca n be alternatively enabled, allowing more accurate digitization for darker areas in the image. in addition to a traditional, parallel logic output the mt9v022 also features a serial low- voltage differential signaling (lvds) output. the sensor can be operated in a stereo- camera, and the sensor, designated as a stereo -master, is able to merge the data from itself and the stereo-slave sensor into one serial lvds stream. the sensor is designed to operate in a wide temperature range (?40c to +85c). figure 1: block diagram parallel video data out serial register i/o control register adcs active-pixel sensor (aps) array 752h x 480v timing and control digital processing analog processing serial video lvds out slave video lvds in (for stereo applications only)
mt9v022_ds rev. l 6/15 en 7 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor general description figure 2: 52-ball ibga package a b c d e f g h 2 ser_ shft_ bypass ser_ v dd d out 7 frame line_ 3 ser_ shft_ lvds d gnd stln_ expo- sure 1 v dd lvds bypass ser_ d out 5 d out 6 d out 8 d out 9 4 v dd v dd s data sclk 6 d out 0 d out 1 d gnd a gnd led_ oe 7 d out 2 d out 4 a gnd nc nc v aa s_ctrl_ rsvd 5 sys- pixclk stfrm_ error top view (ball down) out _valid 8 d out 3 vaapix v aa nc nc stand- reset# s_ctrl dataout _p lvds _clkin _p gnd datain _p clkout _p datain _n valid dataout _n clkout _n gnd out lvds clk out _adr1 adr0 by _clkin _n
mt9v022_ds rev. l 6/15 en 8 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor ball descriptions ball descriptions table 1: ball descriptions only pins d out 0 through d out 9 may be tri-stated. 52-ball ibga numbers symbol type description note h7 rsvd input connect to d gnd .1 d2 ser_datain_n input serial data in for ster eoscopy (differential negative). tie to 1k ? pull-up (to 3.3v) in non-stereoscopy mode. d1 ser_datain_p input serial data in for ster eoscopy (differential positive). tie to d gnd in non-stereoscopy mode. c2 bypass_clkin_n input input bypass shift-clk (differential negative). tie to 1k ? pull-up (to 3.3v) in non-stereoscopy mode. c1 bypass_clkin_p input input bypass shift-clk (differential positive). tie to d gnd in non-stereoscopy mode. h3 exposure input rising edge star ts exposure in slave mode. h4 sclk input two-wire serial interface clock. connect to v dd with 1.5k resistor even when no other two-wire serial interface peripheral is attached. h6 oe input d out enable pad, active high. 2 g7 s_ctrl_adr0 input two-wire serial interface slave address bit 3. h8 s_ctrl_adr1 input two-wire serial interface slave address bit 5. g8 reset# input asynchronous reset. all registers assume defaults. f8 standby input shut down sensor operation for power saving. a5 sysclk input master clock (26.6 mhz). g4 s data i/o two-wire serial interface data. connect to v dd with 1.5k resistor even when no other two-wire serial interface peripheral is attached. g3 stln_out i/o output in master mode ? start line sync to drive slave chip in-phase; input in slave mode. g5 stfrm_out i/o output in master mode ? start frame sync to drive a slave chip in-phase; input in slave mode. h2 line_valid output asserted when d out data is valid. g2 frame_valid output asserted when d out data is valid. e1 d out 5 output parallel pixel data output 5. f1 d out 6 output parallel pixel data output 6. f2 d out 7 output parallel pixel data output 7. g1 d out 8 output parallel pixel data output 8 h1 d out 9 output parallel pixel data output 9. h5 error output error detected. directly connected to stereo error flag. g6 led_out output led strobe output. b7 d out 4 output parallel pixel data output 4. a8 d out 3 output parallel pixel data output 3. a7 d out 2 output parallel pixel data output 2. b6 d out 1 output parallel pixel data output 1. a6 d out 0 output parallel pixel data output 0. b5 pixclk output pixel clock out. d out is valid on rising edge of this clock.
mt9v022_ds rev. l 6/15 en 9 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor ball descriptions notes: 1. pin h7 (rsvd) must be tied to gnd. 2. output enable (oe) tri-states signals d out 0Cd out 9. no other signals are tri-stated with oe. 3. no connect. these pins must be left floating for proper operation. figure 3: typical configuration (connection) ? parallel output mode note: lvds signals are to be left floating. b3 shft_clkout_n output output shift clk (differential negative). b2 shft_clkout_p output output shift clk (differential positive). a3 ser_dataout_n output serial data out (differential negative). a2 ser_dataout_p output serial data out (differential positive). b4, e2 v dd supply digital power 3.3v. c8, f7 v aa supply analog power 3.3v. b8 vaapix supply pixel power 3.3v. a1, a4 v dd lvds supply dedicated power for lvds pads. b1, c3 lvdsgnd ground dedicated gnd for lvds pads. c6, f3 d gnd ground digital gnd. c7, f6 a gnd ground analog gnd. e7, e8, d7, d8 nc nc no connect. 3 table 1: ball descriptions (continued) only pins d out 0 through d out 9 may be tri-stated. 52-ball ibga numbers symbol type description note sysclk line_valid frame_valid pixclk d out (9:0) standby exposure rsvd s_ctrl_adr0 s_ctrl_adr1 lvdsgnd led_out error s data sclk reset# oe v dd lvds a gnd d gnd v dd v aa vaapix master clock 0.1 f to controller standby from controller or digital gnd two-wire serial interface v dd v aa vaapix to led output 10k 1.5k
mt9v022_ds rev. l 6/15 en 10 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor pixel data format pixel data format pixel array structure the mt9v022 pixel array is configured as 782 columns by 492 rows, shown in figure 4. the left 26 columns and the top eight rows of pixels are optically black and can be used to monitor the black level. the black row data is used internally for the automatic black level adjustment. however, the middle four black rows can also be read out by setting the sensor to raw data output mode. there are 753 columns by 481 rows of optically active pixels. the active area is surrounded with optically transparent dummy columns and rows to improve image uniformity within the active area. one additional active column and active row are used to allow horizontally and vertically mirrored readout to also start on the same color pixel. figure 4: pixel array description figure 5: pixel color pattern detail (top right corner) (782,492) 2 dummy columns 2 dummy rows 8 dark, 1 light dummy rows (0,0) 26 dark, 1 light dummy columns pixel (2,9) row readout direction b g b g b g g r g r g r g r g r g r g r g r g r g r g r g r b g b g b g b g b g b g b g b g b g column resdout direction
mt9v022_ds rev. l 6/15 en 11 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor color device limitations color device limitations the color version of the mt9v022 does not support or offers reduced performance for the following functionalities. pixel binning pixel binning is done on immedi ate neighbor pixels only, no facility is provided to skip pixels according to a bayer pattern. therefore, the result of binning combines pixels of different colors. for more information, see ?pixel binning? on page 34. interlaced readout interlaced readout yields one field consisting only of red and green pixels and another consisting only of blue and green pixels. this is due to the bayer pattern of the cfa. automatic black level calibration when the color bit is set (r0x0f[2]=1), the sensor uses green1 pixels black level correc- tion value, which is applied to all colors. to use calibration value based on all dark pixels offset values, the color bit should be cleared. other limiting factors black level correction and row-wise noise correction are applied uniformly to each color. automatic exposure and gain control calculations are made based on all three colors, not just the green luma channel. high dyna mic range does operate; however, on semi- conductor strongly recommends limiting use to linear operation if good color fidelity is required. output data format the mt9v022 image data can be read out in a progressive scan or interlaced scan mode. valid image data is surrounded by horizontal and vertical blanking, as shown in figure 6. the amount of horizontal and vertical bl anking is programmable through r0x05 and r0x06, respectively. line_valid is high during the shaded region of the figure. see ?output data timing? on page 13 for the description of frame_valid timing.
mt9v022_ds rev. l 6/15 en 12 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor output data format figure 6: spatial illustration of image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
mt9v022_ds rev. l 6/15 en 13 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor output data format output data timing the data output of the mt9v022 is sync hronized with the pixclk output. when line_valid is high, one 10-bit pixel datum is output every pixclk period. figure 7: timing example of pixel data the pixclk is a nominally inverted version of the master clock (sysclk). this allows pixclk to be used as a clock to latch the data. however, when column bin 2 is enabled, the pixclk is high for one complete master clock master period and then low for one complete master clock period; when column bin 4 is enabled, the pixclk is high for two complete master clock periods and then low for two complete master clock periods. it is continuously enabled, even during the blanking period. setting r0x74 bit[4] = 1 causes the mt9v022 to invert the polarity of the pixclk. the parameters p1, a, q, and p2 in figure 8 are defined in table 2. figure 8: row timing and frame_valid/line_valid signals table 2: frame time parameter name equation default timing at 26.66 mhz a active data time r0x04 752 pixel clocks = 752 master = 28.20 ? s p1 frame start blanking r0x05 - 23 71 pixel clocks = 71master = 2.66 ? s p2 frame end blanking 23 (fixed) 23 pixel clocks = 23 master = 0.86 ? s q horizontal blanking r0x05 94 pixel clocks = 94 master = 3.52 ? s line_valid pixclk d out (9:0) p 0 (9:0) p 1 (9:0) p2 (9:0) p 3 (9:0) p 4 (9:0) p n-1 (9:0) p n (9:0) valid image data blanking blanking ... ... ... ... p1 a q a q a p2 number of master clocks frame_valid line_valid ... ... ...
mt9v022_ds rev. l 6/15 en 14 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor output data format sensor timing is shown above in terms of pi xel clock and master clock cycles (refer to figure 7 on page 13). the recommended master clock frequency is 26.66 mhz. the vertical blanking and total fr ame time equations assume that the number of integration rows (bits 11 through 0 of r0x0b) is less than the number of active rows plus blanking rows minus overhead rows (r0x03 + r0x06 - 2). if this is not the case, the number of inte- gration rows must be used instead to determ ine the frame time, as shown in table 3. in this example it is assumed that r0x0b is programmed with 523 rows. for simultaneous mode, if the exposure time register (0x0b) exceeds the total readout time, then vertical blanking is internally extended automaticall y to adjust for the additional integration time required. this extended value is not written back to r0x06 (vertical blanking). r0x06 can be used to adjust frame to frame readout time. this register does not effect the exposure time but it may extend the readout time. notes: 1. the mt9v022 uses column parallel analog-digital converters, thus short row timing is not possible. the minimum total row time is 660 columns (horiz ontal width + horizontal blanking). the mini- mum horizontal blanking is 43. when the window width is set below 617, horizontal blanking must be increased. the frame rate will not increase for row times less than 660 columns. a+q row time r0x04 + r0x05 846 pixel clocks = 846 master = 31.72 ? s v vertical blanking (r0x06) x (a + q) + 4 38,074 pixel clocks = 38,074 master = 1.43ms nrows x (a + q) frame valid time (r0x03) (a + q) 406,080 pixel clocks = 406,080 master = 15.23ms f total frame time v + (nrows x (a + q)) 444,154 pixel clocks = 444,154 master = 16.66ms table 3: frame timelong integration time parameter name equation (number of master clock cycles) default timing at 26.66 mhz v vertical blanking (long integration time) (r0x0b + 2 - r0x03) (a + q) + 4 38,074 pixel clocks = 38,074 master = 1.43ms f total frame time (long integration time) (r0x0b + 2) (a + q) + 4 444,154 pixel clocks = 444,154 master = 16.66ms table 2: frame time (continued) parameter name equation default timing at 26.66 mhz
mt9v022_ds rev. l 6/15 en 15 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor serial bus description serial bus description registers are written to and read from the mt9v022 through the two-wire serial inter- face bus. the mt9v022 is a serial interface sl ave with four possible ids (0x90, 0x98, 0xb0 and 0xb8) determined by the s_ctrl_adr0 and s_ctrl_adr1 input pins. data is transferred into the mt9v022 and out through the serial data (s data ) line. the s data line is pulled up to v dd off-chip by a 1.5k ? resistor. either the slave or master device can pull the s data line down?the serial interface pr otocol determines which device is allowed to pull the s data line down at any given time. the registers are 16-bit wide, and can be accessed through 16- or 8-bit two-wire serial interface sequences. protocol the two-wire serial interface defines several different transmission codes, as follows: ?a start bit ? the slave device 8-bit address ? a(n) (no) acknowledge bit ? an 8-bit message ?a stop bit sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device?s 8-bi t address. the last bit of the address deter- mines if the request is a read or a write, wh ere a ?0? indicates a write and a ?1? indicates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the sl ave sends an acknowledge bit to indicate that the register address has been received. the master then tr ansfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. the mt9v022 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register addr ess. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read mode slave addres s. the master then clocks out the register data eight bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. the mt9v022 allows for 8-bit data transfers through the two-wire serial interface by writing (or reading) the most significant 8 bits to the register and then writing (or reading) the least significant 8 bits to r0xf0 (240). bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits.
mt9v022_ds rev. l 6/15 en 16 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor serial bus description start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of 7 bits of address and 1 bit of direction. a ?0? in the lsb of the ad dress indicates write mode, and a ?1? indicates read mode. as indicated above, the mt9v022 allows four possible slave addresses deter- mined by the two input pins, s_ctrl_adr0 and s_ctrl_adr1. data bit transfer one data bit is transferred during each clock pulse. the two-wire serial interface clock pulse is provided by the master. the data must be stable during the high period of the serial clock?it can only change when the two-wire serial interface clock is low. data is transferred 8 bits at a time, fo llowed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence. table 4: slave address modes {s_ctrl_adr1, s_ctrl_adr0} slave address write/read mode 00 0x90 write 0x91 read 01 0x98 write 0x99 read 10 0xb0 write 0xb1 read 11 0xb8 write 0xb9 read
mt9v022_ds rev. l 6/15 en 17 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences two-wire serial interface sample read and write sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 9. a start bit given by the master, followed by the write address, starts the sequence. the image sensor then gives an acknowledge bit and expects the re gister address to come first, followed by the 16-bit data. after each 8-bit the image sensor gives an acknowledge bit. all 16 bits must be written before the register is update d. after 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register. the master stops writing by sending a start or stop bit. figure 9: timing diagram showing a write to r0x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 10. first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is about to happen from the register. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented af ter every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 10: timing diagram showing a re ad from r0x09; returned value 0x0284 sclk s data start ack 0xb8 addr ack ack ack stop r0x09 1000 0100 0000 0010 sclk s data start ack 0xb8 addr 0xb9 addr 0000 0010 r0x09 ack ack ack stop 1000 0100 nack
mt9v022_ds rev. l 6/15 en 18 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences 8-bit write sequence to be able to write 1 byte at a time to the re gister a special register address is added. the 8-bit write is done by first writing the upper 8 bits to the desired register and then writing the lower 8 bits to the special register addres s (r0xf0). the register is not updated until all 16 bits have been written. it is not po ssible to just update half of a register. in figure 11 on page 18, a typical sequence for 8-bit writing is shown. the second byte is written to the special register (r0xf0). figure 11: timing diagram showing a bytewise write to r0x09 with the value 0x0284 8-bit read sequence to read one byte at a time the same special register address is used for the lower byte. the upper 8 bits are read from the desired register. by following this with a read from the special register (r0xf1) the lower 8 bits are accessed (figure 12). the master sets the no- acknowledge bits shown. figure 12: timing diagram showing a bytewis e read from r0x09; returned value 0x0284 stop r0xf0 ack start 0xb8 addr ack s data sclk ack ack ack ack r0x09 0xb8 addr 0000 0010 1000 0100 start start 0xb9 addr s data sclk stop nack ack ack ack r0x09 start 0xb8 addr 0000 0010 start 0xb9 addr s data sclk nack ack ack ack r0xf0 start 0xb8 addr 1000 0100
mt9v022_ds rev. l 6/15 en 19 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor two-wire serial interface sample read and write sequences register lock included in the mt9v022 is a register lock (r0xfe) feature that can be used as a solution to reduce the probability of an inadverten t noise-triggered two-wire serial interface write to the sensor. all registers (or read mo de register?register 13 only) can be locked; it is important to prevent an inadvertent two- wire serial interface write to register 13 in automotive applications since this regist er controls the image orientation and any unintended flip to an image can cause serious results. at power-up, the register lock defaults to a value of 0xbeef, which implies that all registers are unlocked and any two-wire seri al interface writes to the register gets committed. lock all registers if a unique pattern (0xdead) to r0xfe is programmed, any subseque nt two-wire serial interface writes to registers (except r0xfe) are not committed. alternatively, if the user writes a 0xbeef to the register lock re gister, all registers are unlocked and any subsequent two-wire serial interface writes to the register are committed. lock read mode register only (r0x0d) if a unique pattern (0xdeaf) to r0xfe is programmed, any subsequent two-wire serial interface writes to register 13 is not committed. alternatively, if the user writes a 0xbeef to register lock register, register 13 is unlocked and any subsequent two-wire serial interface writes to this register is committed.
mt9v022_ds rev. l 6/15 en 20 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description feature description operational modes the mt9v022 works in master, snapshot, or slave mode. in master mode the sensor generates the readout timing. in snapshot mode it accepts an external trigger to start integration, then generates the readout timi ng. in slave mode the sensor accepts both external integration and readout controls. th e integration time is programmed through the two-wire serial interface during master or snapshot modes, or controlled via exter- nally generated control signal during slave mode. master mode there are two possible operation methods fo r master mode: simultaneous and sequen- tial. one of these operation modes must be se lected via the two-wire serial interface. simultaneous master mode in simultaneous master mode, the exposure period occurs during readout. the frame synchronization waveforms are shown in figure 13 and figure 14. the exposure and readout happen in parallel rather than sequen tial, making this the fastest mode of oper- ation. figure 13: simultaneous master mode synchronization waveforms #1 figure 14: simultaneous master mode synchronization waveforms #2 readout time > exposure time led_out d out (9:0) line_valid frame_valid exposure time vertical blanking xxx xxx xxx exposure time > readout time led_out d out (9:0) line_valid frame_valid exposure time vertical blanking xxx xxx xxx
mt9v022_ds rev. l 6/15 en 21 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description when exposure time is greater than the su m of vertical blank and window height, the number of vertical blank rows is increase d automatically to accommodate the exposure time. sequential master mode in sequential master mode the exposure period is followed by readout. the frame synchronization waveforms for sequential master mode are shown in figure 15. the frame rate changes as the integration time changes. figure 15: sequential master mode synchronization waveforms snapshot mode in snapshot mode the sensor accepts an input trigger signal which initiates exposure, and is immediately followed by readout. figure 16 shows the interface signals used in snapshot mode. in snapshot mode, the start of the integration period is determined by the externally applied exposure pulse that is input to the mt9v022. the integration time is preprogrammed via the two-wire serial interface on r0x0b. after the frame's inte- gration period is complete the readout pr ocess commences and the syncs and data are output. sensor in snapshot mode can captur e a single image or a sequence of images. the frame rate may only be controlled by changing the period of the user supplied exposure pulse train. the frame synchron ization waveforms for snapshot mode are shown in figure 17. figure 16: snapshot mode interface signals led_out d out (9:0) line_valid frame_valid exposure time xxx xxx xxx controller exposure sysclk pixclk line_valid frame_valid d out (9:0) mt9v022
mt9v022_ds rev. l 6/15 en 22 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description figure 17: snapshot mode fr ame synchronization waveforms slave mode in slave mode, the exposure and readout are controlled using the exposure, stfrm_out, and stln_out pins. when the slave mode is enabled, stfrm_out and stln_out become input pins. the start and end of integration are contro lled by exposure and stfrm_out pulses, respectively. while a stfrm_out pulse is used to stop integration, it is also used to enable the readout process. after integration is stopped, the user provid es stln_out pulses to trigger row readout. a full row of data is read out with each stln_out pulse. the user must provide enough time between successive stln_o ut pulses to allow the comp lete readout of one row. it is also important to provide additional st ln_out pulses to allow the sensors to read the vertical blanking rows. it is recommended that the user program the vertical blank register (r0x06) with a value of 4, and ac hieve additional vertic al blanking between frames by delaying the application of the stfrm_out pulse. the elapsed time between the rising edge of stln_out and the first valid pixel data is [horizontal blanking register (r0x05) + 4] clock cycles. figure 18: slave mode operation led_out d out (9:0) line_valid frame_valid exposure time xxx xxx xxx exposure 1-row time 2 master clocks 1-row time 98 master clocks exposure (input) stfrm_out (input) led_out (output) stln_out (input) line_valid (output) integration time vertical blanking (def = 45 lines)
mt9v022_ds rev. l 6/15 en 23 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description signal path the mt9v022 signal path consists of a programmable gain, a pr ogrammable analog offset, and a 10-bit adc. see ?black leve l calibration? on page 30 for the programmable offset operation description. figure 19: signal path on-chip biases adc voltage reference the adc voltage reference is programmed th rough r0x2c, bits 2:0. the adc reference ranges from 1.0v to 2.1v. the default value is 1.4v. the increment size of the voltage reference is 0.1v from 1.0v to 1.6v (r0x2c[2:0] values 0 to 6). at r0x2c[2:0] = 7, the refer- ence voltage jumps to 2.1v. the effect of the adc calibration does not scale with v ref . instead it is a fixed value rela- tive to the output of the analog gain stage. at default, one lsb of calibration equals two lsb in output data (1lsb offset = 2mv, 1lsb adc = 1mv). it is very important to preserve the correct va lues of the other bits in r0x2c. the default register setting is 0x0004. v_step voltage reference this voltage is used for pixel high dynamic range operations, programmable from r0x31 through r0x34. chip version chip version registers r0x 00 and r0xff are read-only. pixel output (reset minus signal) offset correction voltage (r0x48 or result of blc) 10 (12) bit adc adc data (9:0) gain selection (r0x35 or result of agc) v ref (r0x2c) c2 c1
mt9v022_ds rev. l 6/15 en 24 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description window control registers r0x01 column start, r0x02 row star t, r0x03 window height (row size), and r0x04 window width (column size ) control the size and star ting coordinates of the window. the values programmed in the window height and width registers are the exact window height and width out of the sensor. the wind ow start value should never be set below four. to read out the dark rows set bit 6 of r0x0d. in addition, bit 7 of r0x0d can be used to display the dark columns in the image. blanking control horizontal blanking and vertical blanking re gisters r0x05 and r0x06 respectively control the blanking time in a row (horizontal blanking) and between frames (vertical blanking). ? horizontal blanking is specified in terms of pixel clocks. ? vertical blanking is specified in terms of numbers of rows. the actual imager timing can be calculat ed using table 2 on page 13 and table 3 on page 14 which describe ?row timing and frame_valid/line_valid signals.? the minimum number of vertical blank rows is 4. pixel integration control total integration r0x0b total shutter width (in terms of number of rows) this register (along with the window width and horizontal blanking registers) controls the integration time for the pixels. the actual total integration time, t int, is: t int = (number of rows of integration row time) + overhead, where: the number of rows integration is equal to the result of automatic exposure control (aec) which may vary from frame to frame, or, if aec is disabled, the value in r0x0b row time = (r0x04 + r0x05) master clock periods overhead = (r0x04 + r0x05 ? 255) master clock periods typically, the value of r0x0b (total shutter wi dth) is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. if r0x0b is increased beyo nd the total number of rows per frame, it is required to add additional blanking rows using r0x06 as needed. a second constraint is that t int must be adjusted to avoid banding in the image from light flicker. under 60hz flicker, this means frame time must be a multiple of 1/120 of a second. under 50hz flicker, frame time must be a multiple of 1/100 of a second.
mt9v022_ds rev. l 6/15 en 25 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description changes to integration time with automatic exposure control disabled (r 0xaf, bit 0 is cleared to low), and if the total integration time (r0x0b) is changed via the two-wire serial interface while frame_valid is asserted for frame n , the first frame output using the new integration time is frame ( n + 2 ). similarly, when automatic exposu re control is enabled, any change to the integration time for frame n first appears in frame ( n + 2 ) output. the sequence is as follows: 1. during frame n , the new integration time is held in the r0x0b live register. 2. at the start of frame ( n + 1 ), the new integration time is transferred to the exposure control module. integration for each row of frame ( n + 1 ) has been completed using the old integration time. the earliest time that a row can start integrating using the new integration time is immediately afte r that row has been read for frame ( n + 1 ). the actual time that rows start integratin g using the new integration time is depen- dent on the new value of the integration time. 3. when frame ( n + 1 ) is read out, it is integrated using the new integration time. if the integration time is changed (r0x0b written) on successive frames, each value written is applied to a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. however, when automatic exposure control is disabled, if the integration time is changed through the two-wire serial interf ace after the falling edge of frame_valid for frame n , the first frame output using the new integration time becomes frame ( n+3 ). figure 20: latency when changing integration frame_valid image data frame start led_out output image with int = 200 rows output image with int = 300 rows int = 300 rows int = 200 rows int = 200 rows int = 300 rows new integration programmed actual integration
mt9v022_ds rev. l 6/15 en 26 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description exposure indicator the exposure indicator is controlled by: ?r0x1b led_out control the mt9v022 provides an output pin, led_out, to indicate when the exposure takes place. when r0x1b bit 0 is clear, led_out is high during exposure. by using r0x1b, bit 1, the polarity of the led_out pin can be inverted. high dynamic range high dynamic range is controlled by: ? r0x08 shutter width 1 ? r0x09 shutter width 2 ?r0x0a shutter width control ?r0x31 ? r0x34 v_step voltages in the mt9v022, high dynamic range (that is, r0 x0f, bit 6 = 1) is achieved by controlling the saturation level of the pixel (hdr or high dynamic range gate) during the exposure period. the sequence of the control voltages at the hdr gate is shown in figure 21. after the pixels are reset, the step voltage, v_step, which is applied to hdr gate, is setup at v1 for integration time t 1 then to v2 for time t 2 , then v3 for time t 3 , and finally it is parked at v4, which also serves as an antiblooming volt age for the photodetector. this sequence of voltages leads to a piecewise linear pixel response, illustrated (in approximates) in figure 21 on page 26. figure 21: sequence of control voltages at the hdr gate figure 22: sequence of voltages in a piecewise linear pixel response t 2 t 3 v4~0.8v exposure t 1 hdr voltage v aa (3.3v) v1~1.4v v2~1.2v v3~1.0v dv1 dv2 dv3 1/t 1 1/t 2 1/t 3 light intensity output
mt9v022_ds rev. l 6/15 en 27 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description the parameters of the step voltage v_step which takes values v1, v2, and v3 directly affect the position of the knee points in figure 22. light intensities work approximately as a reci procal of the partial exposure time. typi- cally, t 1 is the longest exposure, t 2 shorter, and so on. thus the range of light intensities is shortest for the first slope, providing the highest sensitivity. the register settings for v_step and partial exposures are: v1 = r0x31, bits 4:0 v2 = r0x32, bits 4:0 v3 = r0x33, bits 4:0 v4 = r0x34, bits 4:0 t int = t 1 + t 2 + t 3 there are two ways to specify the knee points timing, the first by ma nual setting (default) and the second by automatic knee point adjustment. when the auto adjust enabler is set to high (low by default), the mt9v022 calculates the knee points automatically using the following equations: t 1 = t int - t 2 - t 3(eq 1) t 2 = t int x (?) r0x0a, bits 3:0 (eq 2) t 3 = t int x (?) r0x0a, bits 7:4 (eq 3) as a default for auto exposure, t 2 is 1/16 of t int, t 3 is 1/64 of t int. when the auto adjust enabler is disabled (default), t 1, t 2, and t 3 may be programmed through the two-wire serial interface: t 1 = r0x08, bits 14:0 (eq 4) t 2 = (r0x09, bits 14:0) - (r0x08, bits 14:0) (eq 5) t 3 = t int - t 1 - t 2(eq 6) t int may be based on the manual setting of r0x0 b or the result of the aec. if the aec is enabled then the auto knee adjust must also be enabled. variable adc resolution by default, adc resolution of the sensor is 10-bit. addition ally, a companding scheme of 12-bit into 10-bit is enabled by the r0x1c (2 8). this mode allows higher adc resolution which means less quantization noise at low-li ght, and lower resolution at high light, where good adc quantization is not so critical because of the high level of the photon?s shot noise.
mt9v022_ds rev. l 6/15 en 28 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description figure 23: 12- to 10-bit companding chart gain settings changes to gain settings when the digital gain settings (r0x80 ? r0x98) are changed, the gain is updated on the next frame start. however, the latency for an analog gain change to take effect depends on the automatic gain control. if automatic gain control is enabled (r0xaf, bit 1 is set to high), the gain changed for frame n first appears in frame ( n + 1 ); if the automatic gain control is disabled, the gain changed for frame n first appears in frame ( n + 2 ). both analog and digital gain change regardless of whether the integration time is also changed simultaneously. figure 24: latency of analog gain change when agc is disabled 256 512 768 1,024 4,096 2,048 1,024 512 256 4 to 1 companding (1,536 384) 8 to 1 companding (2,048 256) 10-bit codes 12-bit codes 2 to 1 companding (256 128) no companding (256 256) frame_valid image data frame start output image with gain = 3.0x output image with gain = 3.5x gain = 3.0x gain = 3.5x gain = 3.0x gain = 3.5x new gain programmed actual gain
mt9v022_ds rev. l 6/15 en 29 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description analog gain analog gain is controlled by: ?r0x35 global gain the formula for gain setting is: gain = bits[6:0] x 0.0625 (eq 7) the analog gain range supported in the mt9v022 is 1x ? 4x with a step size of 6.25 percent. to control gain manually with this register, the sensor must not be in agc mode. when adjusting the luminosity of an im age, it is recommended to alter exposure first and yield to gain increases only when the exposure value has reached a maximum limit. analog gain = bits (6:0) x 0.0625 for values 16?31 analog gain = bits (6:0)/2 x 0.125 for values 32?64 for values 16?31: each lsb increases analog gain 0.0625v/v. a value of 16 = 1x gain. range: 1x to 1.9375x. for values 32?64: each 2 lsb increases analog gain 0.125v/v (that is, double the gain increase for 2 lsb). range: 2x to 4x. odd values do not result in gain increases; the gain increases by 0.125 for values 32, 34, 36, and so on. digital gain digital gain is controlled by: ?r0x99 ? r0xa4 tile coordinates ?r0x80 ? r0x98 tiled digital gain and weight in the mt9v022, the image may be divided into 25 tiles, as shown in figure 25, through the two-wire serial interface, and apply digital gain individually to each tile. figure 25: tiled sample x 0/5 x 1/5 x 2/5 x 3/5 x 5/5 x 5/5 y 0/5 y 1/5 y 2/5 y 3/5 y 4/5 y 5/5 x0_y0 x1_y0 x4_y0 x0_y1 x1_y1 x4_y1 x0_y2 x1_y2 x4_y2 x0_y3 x1_y3 x4_y3 x0_y4 x1_y4 x4_y4
mt9v022_ds rev. l 6/15 en 30 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description registers 0x99 ? 0x9e and 0x9f ? 0xa4 represent the coordinates x 0/5 -x 5/5 and y 0/5 -y 5/5 in figure 25, respectively. digital gains of registers 0x80 ? 0x98 apply to their corresponding tiles. the mt9v022 supports a digital gain of 0.25-3.75x. the formula for digital gain setting is: digital gain = bits[3:0] x 0.25 (eq 8) black level calibration black level calibration is controlled by: ?r0x4c ?r0x42 ? r0x46?r0x48 the mt9v022 has automatic black level calibration on-chip, and if enabled, its result may be used in the offset correction shown in figure 26. figure 26: black level calibration flow chart the automatic black level calibration measures the average value of pixels from 2 dark rows (1 dark row if row bin 4 is enabled) of the chip. (the pixels are averaged as if they were light-sensitive and passed through the appropriate gain.) this row average is then digitally low-pass fi ltered over many frames (r0x47, bits 7:5) to remove temporal noise and random instabil ities associated with this measurement. then, the new filtered average is compar ed to a minimum acceptable level, low threshold, and a maximum accept able level, high threshold. if the average is lower than the minimum acce ptable level, the offset correction voltage is increased by a programmable offset lsb in r0x4c. (default step size is 2 lsb offset = 1 adc lsb at analog gain = 1x.) if it is above the maximum level, the offset correction voltage is decreased by 2 lsb (default). to avoid oscillation of the black level from below to above, the region the thresholds should be programmed so the difference is at least two times the offset dac step size. pixel output (reset minus signal) offset correction voltage (r0x48 or result of blc) 10 (12) bit adc adc data (9:0) gain selection (r0x35 or result of agc) v ref (r0x2c) c2 c1
mt9v022_ds rev. l 6/15 en 31 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description in normal operation, the black level calibration value/offset correction value is calcu- lated at the beginning of each frame and can be read through the two-wire serial inter- face from r0x48. this register is an 8-bit signed two?s complement value. however, if r0x47, bit 0 is set to ?1,? the calibration value in r0x48 may be manually set to override the automatic black level calcul ation result. this feature can be used in conjunction with the ?show dark rows? feature (r0x0d, bit 6) if using an external black level calibration circuit. the offset correction voltage is generated according to the following formulas: offset correction voltage = (8-bit signed two?s complement calibration value,-127 to 127) 0.5mv (eq 9) adc input voltage = (pixel output voltage + offset correction voltage) analog gain (eq 10) row-wise noise correction row-wise noise correction is controlled by the following registers: ?r0x70 row noise control ?r0x72 row noise constant ? r0x73 dark column start when the row-wise noise cancellation algori thm is enabled, the average value of the dark columns read out is used as a correction for the whole row. the row-wise correction is in addition to the general black level correction applied to the whole sensor frame and cannot be used to replace the latter. the dark average is subtracted from each pixel belonging to the same row, and then a positi ve constant is added (r0x72, bits 7:0). this constant should be set to the dark level ta rgeted by the black level algorithm plus the noise expected on the measurements of the averaged values from dark columns; it is meant to prevent clipping from negative noise fluctuations. pixel value = adc value - dark column average + row noise constant (eq 11) on a per-row basis, the dark column aver age is calculated fr om a programmable number of dark columns (pixels) values (r0x70 , bits 3:0). the default is 10 dark columns. of these, the maximum and minimum values are removed and then the average is calcu- lated. if r0x70, bits 3:0 are set to ?0? (2 pixels), it is essentially equivalent to disabling the dark average calculation since the averag e is equal to ?0? after the maximum and minimum values are removed. r0x73 is used to indicate the starting column address of dark pixels which row-noise correction algorithm uses for calculation. in the mt9v022, dark columns which may be used are 759?776. r0x73 is us ed to select the starting column for the calculation. one additional note in setting the row-noise correction register: 777 < (r0x73, bits 9:0) + number of dark pixels programmed in r0x70, bits 3:0 -1 (eq 12) this is to ensure the column pointer does not go beyond the limit the mt9v022 can support.
mt9v022_ds rev. l 6/15 en 32 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description automatic gain control and automatic exposure control the integrated aec/agc unit is responsible fo r ensuring that optimal auto settings of exposure and (analog) gain are computed and updated every frame. aec and agc can be individually enabled or disabled by r0xaf. when aec is disabled (r0xaf[0] = 0), the sensor uses the manual exposure value in r0x0b. when agc is disabled (r0xaf[1] = 0), the se nsor uses the manual gain value in r0x35. see on semi- conductor technical note tn-09-17, ?mt9v022 aec and agc functions,? for further details. figure 27: controllable and observable aec/agc registers the exposure is measured in row-time by reading r0xbb. the exposure range is 1 to 2047. the gain is measured in gain-units by reading r0xba. the gain range is 16 to 63 (unity gain = 16 gain-units; multiply by 1/16 to get the true gain). when aec is enabled (r0xaf[0] = 1), the ma ximum auto exposure value is limited by r0xbd; minimum auto exposure is fixed at 1 row. when agc is enabled (r0xaf[1] = 1), the maximum auto gain value is limited by r0x36; minimum auto gain is fixed to 16 gain-units. the exposure control measures current scene luminosity and desired output luminosity by accumulating a histogram of pixel valu es while reading out a frame. the desired exposure and gain are then calculated from this for subsequent frame. pixel clock speed the pixel clock speed is same as the master clock (sysclk) at 26.66 mhz by default. however, when column binning 2 or 4 (r0x0d , bit 2 or 3) is enab led, the pixel clock speed is reduced by half and one-fourth of the master clock speed respectively. see ?read mode options? on page 34 and ?column binning? on page 35 for additional infor- mation. exp. lpf (r0xa8) 1 0 1 0 exp. skip (r0xa6) manual exp. (r0x0b) aec enable (r0xaf[0]) max. exposure (r0xbd) min exp. aec unit to exposure timing control aec output r0xbb r0xba to analog gain control histogram generator unit agc unit gain lpf (r0xab) gain skip (r0xa9) manual gain (r0x35) agc enable (r0xaf[1]) agc output max. gain (r0x36) min gain desired bin (desired luminance) (r0xa5) current bin (current luminance) (r0xbc) 1 16
mt9v022_ds rev. l 6/15 en 33 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description hard reset of logic the rc circuit for the mt9v022 uses a 10k ?? resistor and a 0.1 ? f capacitor. the rise time for the rc circuit is 1 ? s maximum. soft reset of logic soft reset of logic is controlled by: ?r0x0c reset bit 0 is used to reset the digital logic of the sensor while preserving the existing two-wire serial interface configuration. furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and star ts a new frame. bit 1 is a shadowed reset control register bit to explicitly reset the automatic gain and exposure control feature. these two bits are self-resetting bits and also return to ?0? during two-wire serial inter- face reads. standby control the sensor goes into standby mode by setting standby to high. once the sensor detects that standby is asserted, it comple tes the current frame before disabling the digital logic, internal clocks, and analog power enable signal. to release the sensor out from the standby mode, reset standby back to low. the lvds must be powered to ensure that the device is in standby mode. see "appendix b ? power-on reset and standby timing" on page 54 for more information on standby. monitor mode control monitor mode is controlled by: ? r0x0e monitor mode enable ? r0xc0 monitor mode image capture control the sensor goes into monitor mode when r0x0e bit 0 is set to high. in this mode, the sensor first captures a programmable number of frames (r0xc0), then goes into a sleep period for five minutes. the cycle of sleeping for five minutes and waking up to capture a number of frames continues until r0x0e bit 0 is cleared to return to normal operation. in some applications when monitor mode is enabled, the purpose of capturing frames is to calibrate the gain and exposure of the scene using automatic gain and exposure control feature. this feature typically takes less than 10 frames to settle. in case a larger number of frames is needed, the value of r0xc0 may be increased to capture more frames. during the sleep period, none of the analog ci rcuitry and a very small fraction of digital logic (including a five-minute timer) is powered. the master clock (sysclk) is therefore always required.
mt9v022_ds rev. l 6/15 en 34 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description read mode options (also see ?output data format? on page 11 and ?output data timing? on page 13.) column flip by setting bit 5 of r0x0d the readout order of the columns is reversed, as shown in figure 28 on page 34. row flip by setting bit 4 of r0x0d the readout order of the rows is reversed, as shown in figure 29 on page 34. figure 28: readout of six pixels in normal and column flip output mode figure 29: readout of six rows in normal and row flip output mode pixel binning in addition to windowing mode in which smaller resolution (cif, qcif) is obtained by selecting small window from the sensor array, the mt9v022 also provides the ability to show the entire image captured by pixel array with smaller resolution by pixel binning. pixel binning is based on combining signals from adjacent pixels by averaging. there are two options: binning 2 and binning 4. when bi nning 2 is on, 4 pixel signals from 2 adja- cent rows and columns are combined. in binning 4 mode, 16 pixels are combined from 4 adjacent rows and columns. the image mode may work in conjunction with image flip. the binning operation increases snr but decreases resolution. enabling row bin2 and row bin4 improves frame rate by 2x and 4x respectively. the feature of column binning does not increase the frame rate in less resolution modes. line_valid normal readout d out (9:0) reverse readout d out (9:0) p4,1 (9:0) p4,n (9:0) p4,n-1 (9:0) p4,n-2 (9:0) p4,n-3 (9:0) p4,n-4 (9:0) p4,n-5 (9:0) p4,2 (9:0) p4,3 (9:0) p4,4 (9:0) p4,5 (9:0) p4,6 (9:0) line_valid normal readout d out (9:0) reverse readout d out (9:0) row4 (9:0) row5 (9:0) row6 (9:0) row7 (9:0) row8 7(9:0) row9 (9:0) row484 (9:0) row483 (9:0) row482 (9:0) row481 (9:0) row480 7(9:0) row479 (9:0)
mt9v022_ds rev. l 6/15 en 35 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description row binning by setting bit 0 or 1 of r0x0d, only half or one-fourth of the row set is read out, as shown in figure below. the number of rows read out is half or one-fourth of what is set in r0x03. column binning in setting bit 2 or 3 of r0x0d, the pixel data ra te is slowed down by a factor of either two or four, respectively. this is due to the overhe ad time in the digital pixel data processing chain. as a result, the pixel clock speed is also reduced accordingly. figure 30: readout of 8 pixels in normal and row bin output mode line_valid normal readout d out (9:0) row4 (9:0) row5 (9:0) row6 (9:0) row7 (9:0) row8 (9:0) row9 (9:0) row10 (9:0) row11 (9:0) line_valid row bin 2 readout d out (9:0) row4 (9:0) row6 (9:0) row8 (9:0) line_valid row bin 4 readout d out (9:0) row4 (9:0) row8 (9:0) row10 (9:0)
mt9v022_ds rev. l 6/15 en 36 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description figure 31: readout of 8 pixels in normal and column bin output mode interlaced readout the mt9v022 has two interlaced readout options. by setting r0x07[2:0] = 1, all the even- numbered rows are read out first, followed by a number of programmable field blanking (r0xbf, bits 7:0), and then the odd-number ed rows and finally vertical blanking (minimum is 4 blanking rows). by setting r0x07[2:0] = 2, only one field is read out; consequently, the number of rows read out is half what is set in r0x03. the row start address (r0x02) determines which field gets read out; if the row start address is even, the even field is read out; if row start ad dress is odd, the odd field is read out. line_valid normal readout d out (9:0) pixclk d out (9:0) pixclk d out (9:0) pixclk d1 (9:0) d2 (9:0) d3 (9:0) d4 (9:0) d5 (9:0) d6 (9:0) d7 (9:0) d8 (9:0) line_valid column bin 2 readout d12 (9:0) d34 (9:0) d56 (9:0) d78 (9:0) line_valid column bin 4 readout d out (9:0) d1234 (9:0) d5678 (9:0)
mt9v022_ds rev. l 6/15 en 37 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description figure 32: spatial illustration of interlaced image readout when interlaced mode is enabled, the total number of blanking rows are determined by both field blanking register (r0xbf) and vert ical blanking register (r0x06). the follow- ings are their equations. field blanking = r0xbf, bits 7:0 (eq 13) vertical blanking = r0x06, bits 8:0 -r0xbf, bits 7:0 (eq 14) with minimum vertical blanking requirement = 4 (eq 15) similar to progressive scan, frame_valid is logic low during the valid image row only. binning should not be used in co njunction with interlaced mode. p 4,1 p 4,2 p 4,3 .....................................p 4,n-1 p 4,n p 6,0 p 6,1 p 6,2 .....................................p 6,n-1 p 6,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-2,0 p m-2,2 .....................................p m-2,n-2 p m-2,n p m,2 p m,2 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ............................................................................................. 00 00 00 00 00 00 ............................................................................................. 00 00 00 valid image - even field horizontal blanking vertical blanking p 5,1 p 5,2 p 5,3 .....................................p 5,n-1 p 5,n p 7,0 p 7,1 p 7,2 .....................................p 7,n-1 p 7,n p m-3,1 p m-3,2 .....................................p m-3,n-1 p m-3,n p m,1 p m,1 .....................................p m,n-1 p m,n valid image - odd field field blanking
mt9v022_ds rev. l 6/15 en 38 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description line_valid by setting bit 2 and 3 of r0x74 the line_val id signal can get three different output formats. the formats for reading out four rows and two vertical blanking rows are shown in figure 33. in the last format, the line_val id signal is the xor between the contin- uous line_valid signal and the frame_valid signal. figure 33: different line_valid formats lvds serial (stand-alone/stereo) output the lvds interface allows for the streaming of sensor data serially to a standard off-the- shelf deserializer up to five meters away fr om the sensor. the pixels (and controls) are packeted?12-bit packets for stand-alone mode and 18-bit packets for stereoscopy mode. all serial signalling (clk and data) is lvds. the lvds serial output could either be data from a single sensor (stand-alone) or stream-merged data from two sensors (self and its stereoscopic slave pair). the appendic es describe in detail the topologies for both stand-alone and stereoscopic modes. there are two standard deserializers that can be used. one for a stand-alone sensor stream and the other from a stereoscopic st ream. the deserializer attached to a stand- alone sensor is able to reproduce the standard parallel output (8-bit pixel data, line_valid, frame_valid and pixclk). the de serializer attached to a stereoscopic sensor is able to reproduc e 8-bit pixel data from each sensor (with embedded line_valid and frame_valid) and pixel-clk. an additional (simple) piece of logic is required to extract line_valid and frame_ valid from the 8-bit pixel data. irrespec- tive of the mode (stereoscopy/stand-alone ), line_valid and frame_valid are always embedded in the pixel data. in stereoscopic mode, the two sensors run in lock-step, implying all state machines are in the same state at any given time. this is ensured by the sensor-pair getting their sys- clks and sys-resets in the same instance. configuration writes through the two-wire serial interface are done in such a way th at both sensors can get their configuration updates at once. the inter-sensor serial link is designed in such a way that once the slave pll locks and the data-dly, shft-clk-dly and stream-latency-sel are configured, the master sensor streams good stereo content ir respective of any variation voltage and/or temperature as long as it is within specification. the configuration values of data-dly, shft-clk-dly and stream-latency-sel are either predetermined from the board-layout or can be empirically determined by reading back the stereo-error flag. this flag gets asserted when the two sensor streams are not in sync when merged. the combo_reg is used for out-of-sync diagnosis. default frame_valid line_valid continuously frame_valid line_valid xor frame_valid line_valid
mt9v022_ds rev. l 6/15 en 39 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description figure 34: serial output format for a 6x2 frame notes: 1. external pixel values of 0, 1, 2, 3, are reserved (they only convey control information). any raw pixel of value 0, 1, 2 and 3 will be substituted with 4. 2. the external pixel sequence 1023, 0 1023 is a reserved sequence (conveys control information). any raw pixel sequence of 1023, 0, 1023 w ill be substituted with 1023, 4, 1023. lvds output format in stand-alone mode, the packet size is 12 bits (2 frame bits and 10 payload bits); 10-bit pixels or 8-bit pixels can be selected. in 8-bit pixel mode (r0xb6[0] = 0), the packet consists of a start bit, 8-bit pixel data (with sync codes), the line valid bit, the frame valid bit and the stop bit. for 10-bit pixel mode (r0xb6[0] = 1), th e packet consists of a start bit, 10-bit pixel data, and the stop bit. in stereoscopic mode (see figure 47 on page 52 ), the packet size is 18 bits (2 frame bits and 16 payload bits). the packet consists of a start bit, the master pixel byte (with sync codes), the slave byte (with sync codes), and the stop bit.) table 5: lvds packet format in stand-alone mode (stereoscopy mode bit de-asserted) 12-bit packet use_10-bit_pixels bit de- asserted (8-bit mode) use_10-bit_pixels bit asserted (10-bit mode) bit[0] 1'b1 (start bit) 1'b1 (start bit) bit[1] pixeldata[2] pixeldata[0] bit2] pixeldata[3] pixeldata[1] bit[3] pixeldata[4] pixeldata[2] bit4] pixeldata[5] pixeldata[3] bit[5] pixeldata[6] pixeldata[4] bit[6] pixeldata[7] pixeldata[5] bit[7] pixeldata[8] pixeldata[6] bit[8] pixeldata[9] pixeldata[7] bit[9] line_valid pixeldata[8] bit[10] frame_valid pixeldata[9] bit[11] 1'b0 (stop bit) 1'b0 (stop bit) internal pixclk internal parallel data internal line_valid internal frame_valid external serial data out p 41 p 43 p 42 p 44 p 45 p 46 p 54 p 55 p 56 p 52 p 51 p 53 1023 1023 01p 41 p 42 p 46 2 1 p 44 p 43 p 45 p 51 p 52 p 56 3 p 54 p 53 p 55
mt9v022_ds rev. l 6/15 en 40 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor feature description control signals line_valid and frame_valid can be reconstructed from their respec- tive preceding and succeeding flags that are always embedded within the pixel data in the form of reserved words. when lvds mode is enabled along with column binning (bin 2 or bin 4, r0x0d[3:2], the packet size remains the same but the serial pi xel data stream repeats itself depending on whether 2x or 4x binning is set: ? for bin 2, lvds outputs double the expect ed data (pixel 0,0 is output twice in sequence, followed by pixel 0,1 twice, . . .). ? for bin 4, lvds outputs 4 times the expected data (pixel 0,0 is output 4 times in sequence followed by pixel 0,1 times 4, . . .). the receiving hardware will need to undersam ple the output stream getting data either every 2 clocks (bin 2) or every 4 (bin 4) clocks. if the sensor provides a pixel whose value is 0,1, 2, or 3 (that is, the same as a reserved word) then the outgoing serial pixel value is switched to 4. table 6: lvds packet format in stereosc opy mode (stereoscopy mode bit asserted) 18-bit packet function bit[0] 1'b1 (start bit) bit[1] mastersensorpixeldata[2] bit[2] mastersensorpixeldata[3] bit[3] mastersensorpixeldata[4] bit[4] mastersensorpixeldata[5] bit[5] mastersensorpixeldata[6] bit[6] mastersensorpixeldata[7] bit[7] mastersensorpixeldata[8] bit[8] mastersensorpixeldata[9] bit[9] slavesensorpixeldata[2] bit[10] slavesensorpixeldata[3] bit[11] slavesensorpixeldata[4] bit[12] slavesensorpixeldata[5] bit[13] slavesensorpixeldata[6] bit[14] slavesensorpixeldata[7] bit[15] slavesensorpixeldata[8] bit[16] slavesensorpixeldata[9] bit[17] 1'b0 (stop bit) table 7: reserved words in the pixel data stream pixel data reserved word flag 0 precedes frame valid assertion 1 precedes line valid assertion 2 succeeds line valid de-assertion 3 succeeds frame valid de-assertion
mt9v022_ds rev. l 6/15 en 41 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor electrical specifications electrical specifications table 8: dc electrical characteristics v pwr = 3.3v 0.3v; t a = ambient = 25 c symbol definition condition minimum typical maximum unit v ih input high voltage v pwr - 0.5 C v pwr + 0.3 v v il input low voltage C0.3 C 0.8 v i in input leakage current no pull-up resistor; v in = v pwr or v gnd C15.0 C 15.0 ? a v oh output high voltage i oh = C4.0ma v pwr -0.7 C C v v ol output low voltage i ol = 4.0ma C C 0.3 v i oh output high current v oh = v dd - 0.7 C9.0 C C ma i ol output low current v ol = 0.7 C C 9.0 ma v aa analog power supply default settings 3.0 3.3 3.6 v i pwr a analog supply current default settings C 35.0 60.0 ma v dd digital power supply default settings 3.0 3.3 3.6 v i pwr d digital supply current default settings, c load = 10pf C 35.0 60 ma vaapix pixel array power supply default settings 3.0 3.3 3.6 v i pix pixel supply current default settings 0.5 1.4 3.0 ma v lvds lvds power supply default settings 3.0 3.3 3.6 v i lvds lvds supply current default settings 11.0 13.0 15.0 ma i pwr a standby analog standby supply current stdby = v dd 234 ? a i pwr d standby clock off digital standby supply current with clock off stdby = v dd , clkin = 0 mhz 124 ? a i pwr d standby clock on digital standby supply current with clock on stdby= v dd , clkin = 27 mhz C1.05C ma lvds driver dc specifications |v od | output differential voltage r load = 100 ?? 1% 250 C 400 mv |dv od | change in v od between complementary output states CC50mv v os output offset voltage 1.0 1.2 1.4 mv dv os change in v os between complementary output states CC35mv i os output current when driver shorted to ground ? 10 ? 12 ma i oz output current when driver is tri- state ? 1 ? 10 ? a lvds receiver dc specifications v idth + input differential | v gpd | < 925mv C100 C 100 mv iin input current C C ? 20 ? a
mt9v022_ds rev. l 6/15 en 42 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor electrical specifications notes: 1. this is a stress rating only, and functional op eration of the device at these or any other conditions above those indicated in the operational sect ions of this specific ation is not implied. exposure to absolute maximum rating cond itions for extended periods may affect reliability. notes: 1. the frequency range specified applies on ly to the parallel output mode of operation. propagation delays for pixc lk and data out signals the pixel clock is inverted and delayed relative to the master clock. the relative delay from the master clock (sysclk) rising edge to both the pixel clock (pixclk) falling edge and the data output transition is typically 7n s. note that the falling edge of the pixel clock occurs at approximately the same time as the data ou tput transitions. see table 10 for data setup and hold times. table 9: absolute maximum ratings caution stresses greater than those listed may cause permanent damage to the device. symbol parameter minimum maximum unit v supply power supply voltage (all supplies) C0.3 4.5 v i supply total power supply current C 200 ma i gnd total ground current C 200 ma v in dc input voltage C0.3 v dd + 0.3 v v out dc output voltage C0.3 v dd + 0.3 v t stg 1 storage temperature C40 +125 c table 10: ac electrical characteristics v pwr = 3.3v 0.3v; t a = ambient = 25 c; output load = 10pf symbol definition condition minimum typical maximum unit sysclk input clock frequency note 1 13.0 26.6 27.0 mhz clock duty cycle 45.0 50.0 55.0 % t r input clock rise time 1 2 5 ns t f input clock fall time 1 2 5 ns t plh p sysclk to pixclk propagation delay c load = 10pf 3 7 11 ns t pd pixclk to valid d out (9:0) propagation delay c load = 10pf C2 0 2 ns t sd data setup time 14 16 C ns t hd data hold time 14 16 C t pflr pixclk to line_valid propagation delay c load = 10pf C2 0 2 ns t pflf pixclk to frame_valid propagation delay c load = 10pf C2 0 2 ns
mt9v022_ds rev. l 6/15 en 43 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor electrical specifications propagation delays for frame_valid and line_valid signals the line_valid and frame_valid signals ch ange on the same rising master clock edge as the data output. the line_valid go es high on the same rising master clock edge as the output of the first valid pixel' s data and returns low on the same master clock rising edge as the end of the ou tput of the last valid pixel's data. as shown in the ?output data timing? on page 13, frame_valid goes high 143 pixel clocks before the first line_valid goes hi gh. it returns low 23 pixel clocks after the last line_valid goes low. figure 35: propagation delays for pixclk and data out signals figure 36: propagation delays for frame_valid and line_valid signals t pd t r t f t plh p t hd t sd sysclk pixclk d out (9:0) pixclk frame_valid line_valid t p flf t p flr pixclk frame_valid line_valid
mt9v022_ds rev. l 6/15 en 44 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor electrical specifications performance specifications table 11 summarizes the specificatio n for each performance parameter. notes: 1. all specifications address operation is at t a =25 c ( 3 c) and supply voltage = 3.3v. image sensor was tested without a lens. multiple images were captured and analyzed. setup: vdd = vaa = vaapix = lvdsvdd = 3.3v. te sting was done with default frame timing and default register settings, with the exception of ae c/agc, row noise correction, and auto black level, which were disabled. performance definitions are detailed in the following sections. test 1: sensitivity a flat-field light source (90 lux, color temp erature 4400k, broadband, w/ ir cut filter) is used as an illumination source. signals are measured in lsb on the sensor output. a series of four frames are captured and aver aged to obtain a scal ar sensitivity output code. test 2: dark signal non-uniformity (dsnu) the image sensor is held in the dark. analog gain is changed to the maximum setting of 4x. signals are measured in lsb on the sens or output. a series of four frames are captured and averaged (pixel-by-pixel) into one average frame. dsnu is calculated as the standard deviation of this average frame. test 3: photo response non-uniformity (prnu) a flat-field light source (90 lux, color temperature 4400k, broadband, with ir cut filter) is used as an illumination source. signals are measured in lsb on the sensor output. two series of four frames are captured and averaged (pixel-by-pixel) into one average frame, one series is captured under illuminated conditions, and one is captured in the dark. prnu is expressed as a percentage relating the standard deviation of the average frames difference (illuminated frame - dark frame) to the average illumination level: (eq 16) where s illumination (i) is the signal measured for the i -th pixel from the average illumi- nated frame, s dark (i) is the signal measured for the i -th pixel from the average dark frame, and n p is the total number of pixels contained in the array. table 11: performance specifications parameter unit minimum typical maximum test number sensitivity lsb 400 572 745 1 dsnu lsb n/a 2.3 7.0 2 prnu % n/a 1.3 4.0 3 dynamic range db 52.0 54.4 n/a 4 snr db 33.0 37.3 n/a 5 prnu 100 1 n p ----- - s illumination i ?? s dark i ?? ? ?? 2 i 1 = n p ? 1 n p ----- - s illumination i ?? ?? i 1 = n p ? ----------------- ----------------- ------------------ ------------------ ----------------- - ? =
mt9v022_ds rev. l 6/15 en 45 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor electrical specifications test 4: dynamic range a temporal noise measurement is made with the image sensor in the dark and analog gain changed to the maximum setting of 4x. signals are measured in lsb on the sensor output. two consecutive dark frames are captured. temporal noise is calculated as the average pixel value of the difference frame: (eq 17) where s 1i is the signal measured for the i -th pixel from the first frame, s 2i is the signal measured for the i -th pixel from the second frame, and n p is the total number of pix- els contained in the array. the dynamic range is calculated according to the following formula: (eq 18) where ? t is the temporal noise measured in the dark at 4x gain. test 5: signal-to-noise ratio a flat-field light source (90 lux, color temperature 4400k, broadband, with ir cut filter) is used as an illumination source. signals are measured in lsb on the sensor output. two consecutive illuminated frames are captured . temporal noise is calculated as the average pixel value of the difference frame (according to the formula shown in test 4). the signal-to-noise ratio is calculated as the ratio of the average signal level to the temporal noise according to the following formula: (eq 19) where ? t is the temporal noise measured from the illuminated frames, s 1i is the signal measured for the i -th pixel from the first frame, and n p is the total number of pixels contained in the array. ? i s 1 i s 2 i ? ?? 2 i 1 = n p ? 2 n p ? ----------------- ------------------- = dynamicrange 20 4 1022 ? ? t ----------- --------- - log ? = signal to ? noise ? ratio ?20 s 1 i i 1 = n p ? ?? ?? ?? ?? n p ? ?? ?? ?? ?? ? t -------------------- ----------------- - log ? =
mt9v022_ds rev. l 6/15 en 46 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor electrical specifications two-wire serial bus timing the two-wire serial bus operation requir es certain minimum master clock cycles between transitions. these are specified in the following diagrams in master clock cycles. figure 37: serial host interface start condition timing figure 38: serial host interface stop condition timing notes: 1. all timing are in units of master clock cycle. figure 39: serial host interface data timing for write notes: 1. s data is driven by an off-chip transmitter. figure 40: serial host interface data timing for read notes: 1. s data is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off-chip. sclk 4 s data 4 sclk 4 s data 4 sclk 4 s data 4 sclk 5 s data
mt9v022_ds rev. l 6/15 en 47 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor electrical specifications figure 41: acknowledge signal timing after an 8-bit write to the sensor figure 42: acknowledge signal timing after an 8-bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. temperature reference the mt9v022 contains a temperature reference circuit that can be used to measure rela- tive temperatures. contact yo ur on semiconductor field applications engineer (fae) for more information on using this circuit. sclk sensor pulls down s data pin 6 s data 3 sclk sensor tri-states s data pin (turns off pull down) 7 s data 6
mt9v022_ds rev. l 6/15 en 48 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor electrical specifications figure 43: typical quantum efficiency ? color 0 5 10 15 20 25 30 35 40 350 450 550 650 750 850 950 1050 wavelength (nm) ) % ( y c n e i c i f f e m u t n a u q blue green (b) green (r) red
mt9v022_ds rev. l 6/15 en 49 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor electrical specifications figure 44: typical quantum efficiency ? monochrome 0 10 20 30 40 50 60 350 450 550 650 750 850 950 1050 wavelength (nm) ) % ( y c n e i c i f f e m u t n a u q
mt9v022_ds rev. l 6/15 en 50 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor package dimensions package dimensions figure 45: 52-ball ibga notes: 1. all dimensions in millimeters. seating plane 9.000 0.075 optical area optical center 0.40 (for reference only) 0.90 (for reference only) 5.50 first clear pixel fuses 7.00 1.849 1.999 4.90 1.00 typ 1.00 typ 9.000 0.075 0.375 0.050 0.525 0.050 0.125 (for reference only) c l c l c l c l 7.00 3.50 0.10 a a d c b ball a1 id ball a1 ball a8 52x ?0.55 dimensions apply to solder balls post reflow. the pre- reflow ball is ?0.50 on a ?0.4 nsmd ball pad. encapsulant: epoxy image sensor die lid material: borosilicate glass 0.40 thickness substrate material: plastic laminate solder ball material: 96.5% sn, 3% ag, 0.5% cu maximum rotation of optical area relative to package edges: 1o maximum tilt of optical area relative to package edge : 50 microns. maximum tilt of optical area relative to top of cover glass: 50 microns. d 2.88 ctr 4.512 ctr ?0.15 a b c ?0.15 a c b
mt9v022_ds rev. l 6/15 en 51 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor appendix a C serial configurations appendix a C serial configurations with the lvds serial video output, the dese rializer can be up to 8 meters from the sensor. the serial link can save on the cabling cost of 14 wires (d out [9:0], line_valid, frame_valid, pixclk, gnd). instead, just 3 wires (2 serial lvds, 1 gnd) are sufficient to carry the video signal. configuration of sensor for stand-alo ne serial output with internal pll in this configuration, the internal pll genera tes the shift-clk (x12). the lvds pins ser_- dataout_p and ser_dataout_n must be connected to a deserializer (clocked at approximately the same sy stem clock frequency). figure 46 shows how a standard off-the-sh elf deserializer (national semiconductor ds92lv1212a) can be used to retrieve the standard parallel video signals of d out (9:0), line_valid and frame_valid. figure 46: stand-alone topology typical configuration of the sensor: 1. power-up sensor. 2. enable lvds driver (set r0xb3[4]= 0). 3. de-assert lvds power-down (set r0xb1[1] = 0. 4. issue a soft reset (set r0x0c[0] = 1 followed by r0x0c[0] = 0. if necessary: 5. force sync patterns for the deserializer to lock (set r0xb5[0] = 1). 6. stop applying sync patte rns (set r0xb5[0] = 0). sensor lvds bypass_clkin lvds ser_datain lvds shift_clkout ds92lv1212a 82 line_valid frame_valid pixel lvds ser_dataout 26.6 mhz osc. clk 26.6 mhz osc. 8 meters (maximum) 8-bit configuration shown
mt9v022_ds rev. l 6/15 en 52 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor appendix a C serial configurations configuration of sensor for stereosc opic serial output with internal pll in this configuration the internal pll gener ates the shift-clk (x18) in phase with the system-clock. the lvds pins ser_dataout_p and ser_dataout_n must be connected to a deserializer (clocked at appr oximately the same system clock frequency). figure 47 shows how a standard off-the-shelf de serializer can be used to retrieve back d out (9:2) for both the master and slave sensors. additional logic is required to extract out line_valid and frame_valid embedded within the pixel data stream. figure 47: stereoscopic topology typical configuration of the master and slave sensors: 1. power up the sensors. 2. broadcast write to de-assert lvds power-down (set r0xb1[1] = 0). 3. individual write to master sensor putting its internal pll into bypass mode (set r0xb1[0] = 1). 4. broadcast write to both sensors to set the stereoscopy bit (set r0x07[5] = 1). 5. make sure all resolution, vertical blanki ng, horizontal blanking, window size, and aec/agc configurations are done through broadcast write to maintain lockstep. 6. broadcast write to enable lvds driver (set r0xb3[4] = 0). 7. broadcast write to enable lvds receiver (set r0xb2[4] = 0). 8. individual write to master sensor, putting its internal pll into bypass mode (set r0xb1[0] = 1). 9. individual write to slave sensor, enabli ng its internal pll (set r0xb1[0] = 0). 10. individual write to slave sensor, setting it as a stereo slave (set r0x07[6] = 1). 11. individual writes to mast er sensor to minimize th e inter-sensor skew (set r0xb2[2:0], r0xb3[2:0], and r0xb4[1:0] appropriately). use r0xb7 and r0xb8 to get lockstep feedback from stereo_error_flag. 12. broadcast write to issue a soft reset (set r0x0c[0] = 1 followed by r0x0c[0] = 0). note: the stereo_error_flag is set if a mismatch has occurred at a reserved byte (slave and master sensor?s codes at this reserved byte must match). if the flag is set, steps 11 and 12 are repeated until the stereo_error_flag remains cleared. x 1 8/x 1 2 pl l sensor sensor ds92lv16 8 8 pixel pixel from from slave master sensor slave master 1. pll in non-bypass mode 1. pll in bypass mode 2. pll in x 18 mode (stereoscopy) lv and fv are embedded in the data stream 26.6 mhz osc. lvds ser_datain lvds bypass_clkin lvds ser_datain lvds bypass_clkin lvds shift_clkout lvds ser_dataout 5 meters (maximum) 26.6 mhz osc. lvds ser_dataout lvds shift_clkout
mt9v022_ds rev. l 6/15 en 53 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor appendix a C serial configurations broadcast and individual writes for stereoscopic topology in stereoscopic mode, the two sensors are required to run in lockstep. this implies that control logic in each sensor is in exactly the same state as its pair on every clock. to ensure this, all inputs that affect control lo gic must be identical and arrive at the same time at each sensor. these inputs include: ? system clock ? system reset ? two-wire serial interface clk - scl ? two-wire serial interface data - sda figure 48: two-wire serial interface configuration in stereoscopic mode the setup in figure 48 shows how the two se nsors can maintain lockstep when their configuration registers are written through th e two-wire serial interface. a write to configuration registers would either be broadcast (simultaneous writes to both sensors) or individual (write to just one sensor at a time). reads from configuration registers would be individual (reads from just one sensor at a time). one of the two serial interface slave address bi ts of the sensor is hardwired. the other is controlled by the host. this allows the host to perform either a broadcast or a one-to- one access. broadcast writes are performed by setting the same s_ctrl_adr input bit for both slave and master sensor. individual writ es are performed by setting opposite s_ctrl_adr input bit for both slave and mast er sensor. similarly, individual reads are performed by setting opposite s_ctrl_adr input bit for both slave and master sensor. slave sensor master sensor all system clock lengths (l) must be equal. scl and sda lengths to each sensor (from the host) must also be equal. host launches scl and sda on positive edge of sysclk. scl sda host 26.6 mhz osc. l l l clk s_ctrl_adr[0] clk s_ctrl_adr[0] clk scl scl sda sda
mt9v022_ds rev. l 6/15 en 54 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor appendix b C power-on reset and standby timing appendix b C power-on reset and standby timing reset, clocks, and standby there are no constraints concerning the or der in which the various power supplies are applied; however, the mt9v022 requires reset in order operate properly at power-up. refer to figure 49 for the power-up, reset, and standby sequences. figure 49: power-up, reset, clock and standby sequence notes: 1. all output signals are defined during initial power-up with reset# held low without sysclk being active. to properly reset the rest of the sensor, d uring initial power-up, assert reset# (set to low state) for at least 750ns after all power supplie s have stabilized and sysclk is active (being clocked). driving reset# to low state does not put the part in a low power state. 2. before using two-wire serial interface, wait for 10 sysclk rising edges after reset# is de-asserted. 3. once the sensor detects that standby has been asserted, it completes the current frame readout before entering standby mode. the user must su pply enough sysclks to allow a complete frame readout. see table 2, frame time, on page 13 for more information. 4. in standby, all video data and synchronization output signals are high-z. 5. in standby, the two-wire serial interface is not active. sysclk two-wire serial i/f sclk , s data reset # v dd , v dd lvds, v aa , vaapix data output standby min 10 sysclk cycles pre-standby standby wake up active driven = 0 low-power non-low-power does not respond to serial interface when standby = 1 d out [9:0] power up non-low-power min 20 sysclk cycles min 10 sysclk cycles active power down d out [9:0] note 3 min 10 sysclk cycles
mt9v022_ds rev. l 6/15 en 55 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor appendix b C power-on reset and standby timing standby assertion restrictions standby cannot be asserted at any time. if standby is asserted during a specific window within the vertical blanking pe riod, the mt9v022 may enter a permanent standby state. this window (t hat is, dead zone) occurs prior to the beginning of the new frame readout. the permanent standby stat e is identified by the absence of the frame_valid signal on frame readouts. issuing a hardware reset (reset# set to low state) will return the image sens or to default startup conditions. this dead zone can be avoided by: 1. asserting standby during the valid fram e readout time (frame_valid is high) and maintaining standby assertion for a minimum of one frame period. 2. asserting standby at the end of valid fr ame readout (falling edge of frame_valid) and maintaining standby assertion for a minimum of [5 + r0x06] row-times. when standby is asserted during the vertical blanking period (frame_valid is low ), the standby signal must not change state be tween [vertical blanking register (r0x06) - 5] row-times and [vertical blanking register + 5] row-times after the falling edge of frame_valid. figure 50: standby restricted location frame_valid dead zone 10 row-times vertical blanking period (r0x06) row-times 5 row-times 5 row-times
mt9v022_ds rev. l 6/15 en 56 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor revision history revision history rev. l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/10/15 ? updated ?ordering information? on page 2 rev. k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/16/15 ? updated ?ordering information? on page 2 rev. j. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/30/15 ? converted to on semiconductor template ? updated trademarks rev. h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/10 ? updated to non-confidential rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10 ? updated to aptina template rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/06 ? changed description text in table 1 on pa ge 8, row h5, to "error detected. directly connected to stereo error flag." ? changed text in ?automatic bl ack level calibration? on page 11 ? changed ?writing (or reading) the least sign ificant 8 bits to r0x80 (128)? on page 15 to ?writing (or reading) the least significant 8 bits to r0xf0 (240)? ? changed ?the special register address (r0x f1)? on page 18 to ?t he special register address (r0xf0)? ? changed wording in table 7 on page 15 row 0x00, on page 23 row 0xff, and in table 8 on page 19 row 0x00/0xff from ?rev1,? etc. to ?iter1?, etc. ? updated legal values for r0x08, r0x09, r0x0b in table 8 on page 19 ? updated figure 24: ?latency of analog gain change when agc is disabled,? on page 28 ? changed signal name in table 9 on page 42 in maximum column, vin and vout rows, from vddq to vdd ? moved ?propagation delays for pixclk and data out signals? up to follow table 10 on page 42 ? added section on ?performance specifications? on page 44 ? updated figure 45 ?52-ball ibga? on page 50 ? updated figure 46: ?stand-alone topology,? on page 51 rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/06 ? added "automatic black level calibration" on page 11 ? updated table 8, ?register descri ptions,? on page 19 (r0x73[9:0]) ? updated "automatic gain control and au tomatic exposure control" on page 32 ? updated "row-wise noise correction" on page 31 ? updated table 10, ?ac electrical characteristics,? on page 42 ? updated "appendix a ? serial configurations" on page 51 ? updated "configuration of sensor for stan d-alone serial output with internal pll" on page 51 ? updated figure 46, stand-alone topology, on page 51 ? updated "configuration of sensor for stereo scopic serial output with internal pll" on page 52
mt9v022_ds rev. l 6/15 en 57 ?semiconductor components industries, llc,2015. mt9v022: 1/3-inch wide-vga digital image sensor revision history ? updated figure 47, stereoscopic topology, on page 52 rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/05 ? added lead-free part numbers, page 1 ? added three notes to table 1, ?ball descriptions,? on page 8 ? updated figure 3, typical configuration (connection)?parallel output mode, on page 9 ? updated table 7, ?default register descri ptions,? on page 15. updated registers 0x00, 0x0d, 0xf0, 0xf1 and 0xff. updated registers 0x10, 0x15, 0x20 and 0xc2 with rev 3 default values. ? updated table 8, ?register descriptions,? on page 19 0x00, 0xff ? chip version: added rev 1, 2, and 3 values 0x06 ? vertical blank: minimum number is 4 0x07 ? chip control bit 5 - pll generates 480 mhz clock 0x0d ? added reserve bits [9:8] 0x35 ? added calculation for lower and upper register ranges 0xf0 ? bytewise address register corrected ? added "simultaneous master mode" on page 20 ? added "sequential master mode" on page 21 ? updated "snapshot mode" on page 21 ? updated "slave mode" on page 22 ? updated "pixel clock speed" on page 32 ? added "hard reset of logic" on page 33 ? updated table 8, ?dc electrical characteristics,? on page 41 ? added table 9, ?absolute maximum ratings,? on page 42 ? updated figure 35, propagation delays for pixclk and data out signals, on page 43 ? updated "appendix a ? serial configurations" on page 51 ? updated figure 46, stand-alone topology, on page 51 ? updated figure 47, stereoscopic topology, on page 52 ? added "appendix b ? power-on reset and standby timing" on page 54 rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/05 ? several text changes ? corrected steps in ?configuration of sens or for stereoscopic serial output with internal pll? on page 52 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/05 ? updated part number and header on each page ? updated table 1, ?key performance parame ters,? on page 1 (power consumption). ? updated figure 1, block diagram, on page 6; update ?general description? on page 6 ? updated table 1, ?ball descriptions,? on page 8 ? updated table 7, ?default register descriptions,? on page 15 (0xbe - reserved) ? updated table 8, ?register descriptions,? on page 19 (r0x7f, r0x07[1:0], r0xb2[4], 0xb3[4], 0xba, remove 0xbe) ? updated ?pixel integration control? on page 24 ? updated table 8, ?dc electrical characteristics,? on page 41 ? updated table 10, ?ac electrical characteristics,? on page 42 ? replaced ?thermometer? section and figure with section titled ?temperature refer- ence? on page 47 ? added figure 45, 52-ball ibga, on page 50
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9v022: 1/3-inch wide-vga digital image sensor revision history mt9v022_ds rev. l 6/15 en 58 ?semiconductor components industries, llc,2015 . rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/05 ?initial release

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